Some implementations of an antenna array utilizing thin film transistor (TFT) manufacturing processes have limitations in the refresh rate of the array due to use of high-birefringence liquid crystal (LC) with concomitant low voltage holding ratio. That is, the low voltage holding ratio occurs at the same time as the limitations in the refresh rate of the array due to the high-birefringence LC. To compensate for this, a large storage capacitor is often required to prevent excessive voltage drop. A large storage capacitor in combination with the poor channel resistance, Rds, of typical amorphous silicon TFTs results in large charging time constants, which prevents refresh rates that achieve antenna tracking rate requirements.
More specifically, one way to generate an LC alternating current (AC) drive voltage in the standard matrix architecture is to charge each LC cell with a positive voltage, address each row sequentially, then to charge the LC cell with a negative voltage, and then again addressing each row sequentially at a rate fast enough to maintain the desired LC drive frequency. This method requires updating the matrix at a rate of the drive frequency times the number of rows. This method becomes a challenge as the time to charge the LC cell and storage capacitor increases. The value of the storage capacitance that sets this charge time is determined by the TFT parasitic gate capacitance and its effect on the LC “kickback” voltage. To minimize the kickback voltage, the storage capacitance may need to be large. However, a large storage capacitance means a large charging time, and thus lower refresh rates.